1. Field of the Invention
This invention relates to digital circuits and more particularly to digital circuits wherein metastability oscillation occurs.
2. Description of the Relevant Art
Metastability is a well-known problem that occurs when two or more asynchronous input signals are asserted simultaneously to initiate a response by a given digital system that receives the input signals. The problem arises since the digital system receiving the asserted input signals is configured such that it can receive and process only one asserted input signal at a time. In such a situation, one of the asserted input signals must be determined as the "winner"; that is, one of the signals must override the other simultaneously asserted signals. The asynchronous input signals may be either control or data signals. Typically, the asynchronous input signals are provided to several cross-coupled logic gates such as NAND gates that provide output signals indicative of the "winner" of the asserted input signals. In the situation where only one input signal is asserted at a time, the output signal does not oscillate. However, when the asynchronous input signals are asserted simultaneously, the output signals of the cross-coupled NAND gates oscillate synchronously until becoming unsynchronized due to the inherently different delay characteristics of the logic gates. This oscillation period is known as the metastability period. A stable output signal is thereafter provided at an output line of one of the NAND gates. Unfortunately, during the metastability period, adverse effects can be triggered within the digital system receiving the oscillating output signals. It is therefore desirable to eliminate the adverse effects of metastability oscillation.
One method used to eliminate the adverse effects of metastability oscillation involves the filtering of the metastable inputs by using flip-flops as shown in FIG. 1. Unfortunately, the system of FIG. 1 causes the asynchronous signal generated at the output of the state machine 5 to be delayed by one clock cycle. If metastability persists more than one clock cycle, the system will fail. In addition, the circuit does not guarantee a winner. If both inputs are true simultaneously, a winner is chosen at random or by priority.
Another technique is known as arbitration. This technique involves the generation of a timing pulse window when one or more signals request control. Pre-assigned priorities within the timing pulse window determines the winner. This technique is slow and requires a priority encoder. In addition, the system requires a clock signal and the synchronization of several signals.